The present invention relates to error correction coding (ECC), and more specifically, to selective error coding.
In some applications, writing to memory includes writing to one of multiple memory devices. For example, a server memory is comprised of a number of memory devices such as dynamic random-access memory (DRAM) chips. Writing data to memory of the server typically involves writing to multiple DRAM chips. To ensure that data is correctly written and retrieved, ECC bits are generally written along with the data so that the ECC bits may be verified in the read data. The ECC bits are included with stored data through an encoding process and are verified in read data through a decoding process. Processing of the ECC bits by a decoder may lead to the inclusion of a chip mark. The chip mark identifies one of the DRAMs and indicates that all data from that DRAM must be corrected. Processing of the ECC bits may also lead to the inclusion of a symbol mark. A symbol is a subset of the addresses of one DRAM. The number of addresses in a range defined as a symbol may differ based on the memory device. Thus, the symbol mark identifies that data from a subset of addresses of one of the DRAMs must be corrected.